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| author | AngeloGioacchino Del Regno <[email protected]> | 2024-11-04 12:49:35 +0100 |
|---|---|---|
| committer | Krzysztof Wilczyński <[email protected]> | 2024-11-06 19:57:26 +0000 |
| commit | b609a15e7969d6a50d65067ee783b5d9365b04dd (patch) | |
| tree | 6df49c9216e2d00f192315d69761faa3a876a59e /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py | |
| parent | ade7da14954a5d1003ceb316a230189c445ba357 (diff) | |
PCI: mediatek-gen3: Add support for restricting link width
Add support for restricting the port's link width by specifying
the num-lanes devicetree property in the PCIe node.
The setting is done in the GEN_SETTINGS register (in the driver
named as PCIE_SETTING_REG), where each set bit in [11:8] activates
a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Fei Shao <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py')
0 files changed, 0 insertions, 0 deletions