diff options
| author | Mauro Carvalho Chehab <[email protected]> | 2021-10-21 11:45:11 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2021-11-04 14:32:21 -0500 |
| commit | b22dbbb24571c052364f476381dbac110bdca4d5 (patch) | |
| tree | d6c82a1bfdffb264549eec82556cef6695369ff3 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py | |
| parent | d19afe7be12689bb9ca245122ec5118c3f976e2e (diff) | |
PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
On HiKey970, there's a PEX 8606 PCI bridge on its PHY with 6 lanes. Only 4
lanes are connected:
lane 0 - connected to Kirin 970 (upstream)
lane 4 - M.2 slot
lane 5 - mini PCIe slot
lane 6 - on-board Ethernet controller
Each lane has its own PERST# GPIO pin and needs a clock request.
Add support to parse a DT schema containing the above data.
HiKey 970 requires a little more waiting time for the PCI bridge - which is
outside the SoC - to finish the PERST# reset, and then initialize the eye
diagram.
Increase the waiting time for the PERST# signals accordingly.
[bhelgaas: squash refcount fix from Wan Jiabing <[email protected]>:
https://lore.kernel.org/r/[email protected]
and drop "parent" refcount per
https://lore.kernel.org/all/20211103143059.GA683503@bhelgaas/]
Link: https://lore.kernel.org/r/bb391a0e0f0863b66e645048315fab1a4f63f277.1634812676.git.mchehab+huawei@kernel.org
Link: https://lore.kernel.org/all/9a365cffe5af9ec5a1f79638968c3a2efa979b65.1634622716.git.mchehab+huawei@kernel.org/
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Xiaowei Song <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py')
0 files changed, 0 insertions, 0 deletions