diff options
| author | Nicolin Chen <[email protected]> | 2014-05-06 16:56:00 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2014-05-12 23:13:13 +0100 |
| commit | 57ebbcafab0ce8cce4493c6a243ecdd7066e6ef1 (patch) | |
| tree | f1c3fc761b5e43b85d319f580f9f04991125154d /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py | |
| parent | 89e47f62cf3eea7ad5e3d7d72ea846be37d6e352 (diff) | |
ASoC: fsl_esai: Only bypass sck_div for EXTAL source
ESAI can only output EXTAL clock source directly. But for FSYS clock source,
ESAI can not output it without getting through PSR PM dividers.
So this patch adds an extra check in the code.
Signed-off-by: Nicolin Chen <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py')
0 files changed, 0 insertions, 0 deletions