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authorIlija Hadzic <[email protected]>2013-01-02 18:27:43 -0500
committerAlex Deucher <[email protected]>2013-01-31 16:24:43 -0500
commit40592a17b8747903be95338f461573916a71d739 (patch)
tree0255123d601f1be2c11322ecabdcc368b81a1b16 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py
parent9ffb7a6dca4fd260db91c808efd4d5c56057600c (diff)
drm/radeon: refactor vline packet parsing function
vline packet parsing function for R600 and Evergreen+ are the same, except that they use different registers. Factor out the algorithm into a common function that uses register table passed from ASIC-specific caller. This reduces ASIC-specific function to (trivial) setup of register table and call into the common function. Signed-off-by: Ilija Hadzic <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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