diff options
| author | Jani Nikula <[email protected]> | 2021-08-23 19:18:10 +0300 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2021-08-24 11:02:31 +0300 |
| commit | 1db18260f15315e206469391d5b5e3427be55ad3 (patch) | |
| tree | 3673431cbe55baa472996a95f06e364d38df7a21 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py | |
| parent | 59821ed9c4a63de051042d71526d7bb4eac0617b (diff) | |
drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW
Add the registers for specifying the lower and higher 24 bits of the DP
2.0 pixel clock frequency in Hz.
Bspec: 53326
Reviewed-by: Manasi Navare <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/9047f10318a30bc03ce8516ee3f5512437a95663.1629735412.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py')
0 files changed, 0 insertions, 0 deletions