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author | Andre Przywara <andre.przywara@arm.com> | 2024-02-19 15:36:35 +0000 |
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committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2024-03-11 17:14:46 +0100 |
commit | d7bf0a1ada00021a09dca328e084f77d97ff13b4 (patch) | |
tree | 23b290d29d77dc13d9db0ea496ce0a09141175ec /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
parent | d1dc7ee560154c5e96f874796098c4cb391d5952 (diff) |
thermal/drivers/sun8i: Explain unknown H6 register value
So far we were ORing in some "unknown" value into the THS control
register on the Allwinner H6. This part of the register is not explained
in the H6 manual, but the H616 manual details those bits, and on closer
inspection the THS IP blocks in both SoCs seem very close:
- The BSP code for both SoCs writes the same values into THS_CTRL.
- The reset values of at least the first three registers are the same.
Replace the "unknown" value with its proper meaning: "acquire time",
most probably the sample part of the sample & hold circuit of the ADC,
according to its explanation in the H616 manual.
No functional change, just a macro rename and adjustment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
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