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authorOndrej Jirman <megous@megous.com>2019-04-13 18:54:13 +0200
committerLinus Walleij <linus.walleij@linaro.org>2019-04-23 12:31:42 +0200
commitcc62383fcebe7f03c274462790fd912f4346304b (patch)
tree4c240ae16567212ec6d50baac257bba55c0e5da7 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
parentf7275345728a0ff18a0607dd3706f2ca25dc53e0 (diff)
pinctrl: sunxi: Support I/O bias voltage setting on H6
H6 SoC has a "pio group withstand voltage mode" register (datasheet description), that needs to be used to select either 1.8V or 3.3V I/O mode, based on what voltage is powering the respective pin banks and is thus used for I/O signals. Add support for configuring this register according to the voltage of the pin bank regulator (if enabled). This is similar to the support for I/O bias voltage setting patch for A80 and the same concerns apply. See: commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions