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authorAidan MacDonald <[email protected]>2022-10-26 20:43:42 +0100
committerStephen Boyd <[email protected]>2022-10-27 11:59:05 -0700
commitc799a77720dd350fd742a99d80139514a0b4df4d (patch)
tree1014708eb544874800f81c1a3208ae80efeff800 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
parentd84bf9d6308e2606b60bb5b4577f8b9ac295cf0b (diff)
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be updated alongside the main one, which is needed to handle the I2S divider on some SoCs. Signed-off-by: Aidan MacDonald <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Paul Cercueil <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
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