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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:10:08 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:10:08 -0700 |
| commit | b8e00bdf253e0f0f3a7c351463bdbca513b21900 (patch) | |
| tree | 61b04e2bea6a195ca259999d6ae5dd47f3c16841 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 886516fae2b73a1578600e95631436785f3e44d6 (diff) | |
| parent | f4cc33e78ba8624a79ba8dea98ce5c85aa9ca33c (diff) | |
Merge tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip into for-next
INTC changes to consume for RISCV
* tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
irqchip/riscv-intc: Allow large non-standard interrupt number
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions