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| author | Wills Wang <[email protected]> | 2015-12-20 12:55:23 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2016-02-06 22:46:17 -0800 |
| commit | b7ed5161f17a39ed09fd799a919b5f6de688251d (patch) | |
| tree | 7c7c84442139a5217ea4bc8e853fc9c5a138ed38 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | b78cd1691404ca26ea7ede3d899b8bd2482da745 (diff) | |
sc16is7xx: fix incorrect register bits macro
In datasheet, Modem Status Register MSR[4-7] reflect the modem pins
CTS/DSR/RI/CD signal state.
Signed-off-by: Wills Wang <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions