diff options
| author | Manikanta Maddireddy <[email protected]> | 2019-06-18 23:31:57 +0530 |
|---|---|---|
| committer | Lorenzo Pieralisi <[email protected]> | 2019-06-20 17:40:48 +0100 |
| commit | b5b4717ea0ddf64357c68a865f652487b9b1cdf8 (patch) | |
| tree | 6319e8290f2cc0c72df025cb42b6262f6536e1ef /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | eef4a35026613ff1576ca93a9b158e774330576b (diff) | |
PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20
Cacheable upstream transactions are supported in Tegra20 and Tegra186
only.
AFI_CACHE_BAR_{0,1}_{ST,SZ} registers are available in Tegra20 to
support cacheable upstream transactions. In Tegra186, AFI_AXCACHE
register is defined instead of AFI_CACHE_BAR_{0,1}_{ST,SZ} to be in line
with its memory subsystem design.
Therefore, program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20.
Signed-off-by: Manikanta Maddireddy <[email protected]>
[[email protected]: updated commit log]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions