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authorStephen Boyd <[email protected]>2013-03-18 19:44:15 +0100
committerRussell King <[email protected]>2013-03-22 17:16:55 +0000
commit8164f7af88d9ad3a757bd14f634b23997ee77f6b (patch)
treeea2167af388b04168361423132ea7b188f0b0945 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
parentc40e3641670eb6ebfdb71d4b0c775416ef95f4f0 (diff)
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
The ISAR0 register indicates support for the SDIV and UDIV instructions in both the Thumb and ARM instruction set. Read the register to detect the supported instructions and update the elf_hwcap mask as appropriate. This is better than adding more and more cpuid checks in proc-v7.S for each new cpu variant that supports these instructions. Acked-by: Will Deacon <[email protected]> Cc: Stepan Moskovchenko <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
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