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| author | Paul Cercueil <[email protected]> | 2020-05-15 12:43:36 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2020-05-18 16:51:37 -0700 |
| commit | 4e399b3ba8b937aaa49df836117ce4dc39bf3fcd (patch) | |
| tree | bf9324208aed8081089a955e8878c9e9d262f451 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 25f9f5a2107fdc6510463be4e55012d17d83ab2b (diff) | |
dt-bindings: Document JZ47xx VPU auxiliary processor
Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
Ingenic is a second Xburst MIPS CPU very similar to the main core.
This document describes the devicetree bindings for this auxiliary
processor.
Signed-off-by: Paul Cercueil <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
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