diff options
| author | Will Deacon <[email protected]> | 2013-02-04 12:12:33 +0000 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2013-02-11 18:16:41 +0000 |
| commit | 3a0310eb369aae985d6409d8ff1340146578e5c1 (patch) | |
| tree | 8b1796a500d2dd694c924a57ee4502f31b15ef8b /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | c0e01d5d8f15c085236df184e5bc3d79a8b700cd (diff) | |
arm64: atomics: fix grossly inconsistent asm constraints for exclusives
Our uses of inline asm constraints for atomic operations are fairly
wild and varied. We basically need to guarantee the following:
1. Any instructions with barrier implications
(load-acquire/store-release) have a "memory" clobber
2. When performing exclusive accesses, the addresing mode is generated
using the "Q" constraint
3. Atomic blocks which use the condition flags, have a "cc" clobber
This patch addresses these concerns which, as well as fixing the
semantics of the code, stops GCC complaining about impossible asm
constraints.
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions