diff options
| author | Catalin Marinas <[email protected]> | 2021-04-09 18:37:10 +0100 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2021-04-12 13:38:45 +0100 |
| commit | 2decad92f4731fac9755a083fcfefa66edb7d67d (patch) | |
| tree | 954e29baf4bce155777502117ff6cb26272ea2e4 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 185f2e5f51c2029efd9dd26cceb968a44fe053c6 (diff) | |
arm64: mte: Ensure TIF_MTE_ASYNC_FAULT is set atomically
The entry from EL0 code checks the TFSRE0_EL1 register for any
asynchronous tag check faults in user space and sets the
TIF_MTE_ASYNC_FAULT flag. This is not done atomically, potentially
racing with another CPU calling set_tsk_thread_flag().
Replace the non-atomic ORR+STR with an STSET instruction. While STSET
requires ARMv8.1 and an assembler that understands LSE atomics, the MTE
feature is part of ARMv8.5 and already requires an updated assembler.
Signed-off-by: Catalin Marinas <[email protected]>
Fixes: 637ec831ea4f ("arm64: mte: Handle synchronous and asynchronous tag check faults")
Cc: <[email protected]> # 5.10.x
Reported-by: Will Deacon <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Vincenzo Frascino <[email protected]>
Cc: Mark Rutland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions