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author | André Draszik <[email protected]> | 2024-05-07 15:14:44 +0100 |
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committer | Vinod Koul <[email protected]> | 2024-06-12 16:47:28 +0530 |
commit | 2a0dc34bab8ede5fa50378ef206f580303eed8de (patch) | |
tree | 412212381a19ca5411292dcc1cb0dcdf772acbbb /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
parent | 2f2f5c13cc5ea87f1dd2debfd06fe5f624e5c0fd (diff) |
phy: exynos5-usbdrd: uniform order of register bit macros
Most of the macros are ordered high -> low, but there are some
outliers.
Order them all uniformly from high to low. This will allow adding
additional register (field) definitions in a consistent way.
While at it, also remove some extra empty lines to group register bit
field definitions together with the relevant register. This makes the
registers easier to distinguish visually.
No functional change.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions