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| author | Sean Anderson <[email protected]> | 2024-06-28 16:55:38 -0400 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2024-07-02 18:48:09 +0530 |
| commit | 235d8b663ab9e6cc13f8374abfffa559f50b57b6 (patch) | |
| tree | a2dd5b83d41a7aab4377f747656acb324373ec5c /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 (diff) | |
phy: zynqmp: Only wait for PLL lock "primary" instances
For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.
The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions