diff options
| author | Vincent Minet <[email protected]> | 2014-07-05 01:51:33 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <[email protected]> | 2014-07-07 01:24:24 +0200 |
| commit | 179e8471673ce0249cd4ecda796008f7757e5bad (patch) | |
| tree | ebeb2a6091ccb06272177d147643f95ac345daa5 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 41629a8233470325bfbb60377f555f9e8acc879f (diff) | |
intel_pstate: Set CPU number before accessing MSRs
Ensure that cpu->cpu is set before writing MSR_IA32_PERF_CTL during CPU
initialization. Otherwise only cpu0 has its P-state set and all other
cores are left with their values unchanged.
In most cases, this is not too serious because the P-states will be set
correctly when the timer function is run. But when the default governor
is set to performance, the per-CPU current_pstate stays the same forever
and no attempts are made to write the MSRs again.
Signed-off-by: Vincent Minet <[email protected]>
Cc: All applicable <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions