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authorShashank Sharma <shashank.sharma@intel.com>2015-09-23 23:27:17 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-10-02 14:44:41 +0200
commit11b8e4f58e1baa94e44400a076b1a3757612ea55 (patch)
tree0c70c85e08569c7ca6c3c457d992691d61f96706 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
parent37ab0810c9b7e06ec3904c186c46e9c540b3793b (diff)
drm/i915/bxt: Program Tx Rx and Dphy clocks
BXT DSI clocks are different than previous platforms. So adding a new function to program following clocks and dividers: 1. Program variable divider to generate input to Tx clock divider (Output value must be < 39.5Mhz) 2. Select divide by 2 option to get < 20Mhz for Tx clock 3. Program 8by3 divider to generate Rx clock v2: Fixed Jani's review comments. Adjusted the Macro definition as per convention. Simplified the logic for bit definitions for MIPI PORT A and PORT C in same registers. v3: Refactored the macros for TX, RX Escape and DPHY clocks as per Jani's suggestion. v4: Addressed Jani's review comments. Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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