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| author | Ville Syrjälä <[email protected]> | 2021-07-15 12:35:25 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2021-08-25 17:11:10 +0300 |
| commit | 98b27e79898b5f5a15734525c7a31f67f7a9766a (patch) | |
| tree | 7445ab7f3ff3add0c753f2118421cde9d59ba678 /tools/perf/scripts/python/Perf-Trace-Util/Context.c | |
| parent | 510e890e8222443bbfc74083cb8e0797665fcaaa (diff) | |
drm/i915: Program DPLL P1 dividers consistently
On g4x and pch the DPLL has two P1 dividers (for refresh rate
switching). Program the FPx1 P1 divider consistently to the reduced
clock P1 divider if available, otherwise just program it to the
same value as the FPx0 P1 divider.
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/Context.c')
0 files changed, 0 insertions, 0 deletions