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authorIan Rogers <irogers@google.com>2024-06-20 11:17:17 -0700
committerNamhyung Kim <namhyung@kernel.org>2024-06-20 16:52:24 -0700
commit19121e877c9c840862cda9f45e429bb9e597646f (patch)
tree9f6eb0b5502d63dcf13f530d145a91a90bd10b73 /tools/perf/pmu-events/arch/x86
parent72da747ddd89862ac3ac7dbb17993937a27f5272 (diff)
perf vendor events: Add bonnell counter information
Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1 and later patches. Co-authored-by: Weilin Wang <weilin.wang@intel.com> Co-authored-by: Caleb Biggers <caleb.biggers@intel.com> Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240620181752.3945845-4-irogers@google.com
Diffstat (limited to 'tools/perf/pmu-events/arch/x86')
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/cache.json93
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/counter.json7
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/floating-point.json32
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/frontend.json11
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/memory.json19
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/other.json56
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/pipeline.json44
-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json15
8 files changed, 277 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
index 1ca95a70d48a..86582bb8aa39 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "L1 Data Cacheable reads and writes",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ALL_CACHE_REF",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "L1 Data reads and writes",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ALL_REF",
"SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "Modified cache lines evicted from the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.EVICT",
"SampleAfterValue": "200000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1 Cacheable Data Reads",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.LD",
"SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "L1 Data line replacements",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.REPL",
"SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "Modified cache lines allocated in the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.REPLM",
"SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "L1 Cacheable Data Writes",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ST",
"SampleAfterValue": "2000000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "Cycles L2 address bus is in use.",
+ "Counter": "0,1",
"EventCode": "0x21",
"EventName": "L2_ADS.SELF",
"SampleAfterValue": "200000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.E_STATE",
"SampleAfterValue": "200000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.I_STATE",
"SampleAfterValue": "200000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.MESI",
"SampleAfterValue": "200000",
@@ -78,6 +89,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.M_STATE",
"SampleAfterValue": "200000",
@@ -85,6 +97,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.S_STATE",
"SampleAfterValue": "200000",
@@ -92,6 +105,7 @@
},
{
"BriefDescription": "Cycles the L2 cache data bus is busy.",
+ "Counter": "0,1",
"EventCode": "0x22",
"EventName": "L2_DBUS_BUSY.SELF",
"SampleAfterValue": "200000",
@@ -99,6 +113,7 @@
},
{
"BriefDescription": "Cycles the L2 transfers data to the core.",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "L2_DBUS_BUSY_RD.SELF",
"SampleAfterValue": "200000",
@@ -106,6 +121,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
+ "Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
@@ -113,6 +129,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
+ "Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
@@ -120,6 +137,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
+ "Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
@@ -127,6 +145,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
+ "Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
@@ -134,6 +153,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
+ "Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
@@ -141,6 +161,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@@ -148,6 +169,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@@ -155,6 +177,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@@ -162,6 +185,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@@ -169,6 +193,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@@ -176,6 +201,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -183,6 +209,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -190,6 +217,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -197,6 +225,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -204,6 +233,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -211,6 +241,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -218,6 +249,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -225,6 +257,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -232,6 +265,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -239,6 +273,7 @@
},
{
"BriefDescription": "L2 cache reads",
+ "Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -246,6 +281,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
+ "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
@@ -253,6 +289,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
+ "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
@@ -260,6 +297,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
+ "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
@@ -267,6 +305,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
+ "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
@@ -274,6 +313,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
+ "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
@@ -281,6 +321,7 @@
},
{
"BriefDescription": "L2 cache misses.",
+ "Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.ANY",
"SampleAfterValue": "200000",
@@ -288,6 +329,7 @@
},
{
"BriefDescription": "L2 cache misses.",
+ "Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.DEMAND",
"SampleAfterValue": "200000",
@@ -295,6 +337,7 @@
},
{
"BriefDescription": "L2 cache misses.",
+ "Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.PREFETCH",
"SampleAfterValue": "200000",
@@ -302,6 +345,7 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
+ "Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
@@ -309,6 +353,7 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
+ "Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
@@ -316,6 +361,7 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
+ "Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
@@ -323,6 +369,7 @@
},
{
"BriefDescription": "L2 locked accesses",
+ "Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.E_STATE",
"SampleAfterValue": "200000",
@@ -330,6 +377,7 @@
},
{
"BriefDescription": "L2 locked accesses",
+ "Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.I_STATE",
"SampleAfterValue": "200000",
@@ -337,6 +385,7 @@
},
{
"BriefDescription": "L2 locked accesses",
+ "Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.MESI",
"SampleAfterValue": "200000",
@@ -344,6 +393,7 @@
},
{
"BriefDescription": "L2 locked accesses",
+ "Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.M_STATE",
"SampleAfterValue": "200000",
@@ -351,6 +401,7 @@
},
{
"BriefDescription": "L2 locked accesses",
+ "Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.S_STATE",
"SampleAfterValue": "200000",
@@ -358,6 +409,7 @@
},
{
"BriefDescription": "L2 cache line modifications.",
+ "Counter": "0,1",
"EventCode": "0x25",
"EventName": "L2_M_LINES_IN.SELF",
"SampleAfterValue": "200000",
@@ -365,6 +417,7 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
+ "Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
@@ -372,6 +425,7 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
+ "Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
@@ -379,6 +433,7 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
+ "Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
@@ -386,6 +441,7 @@
},
{
"BriefDescription": "Cycles no L2 cache requests are pending",
+ "Counter": "0,1",
"EventCode": "0x32",
"EventName": "L2_NO_REQ.SELF",
"SampleAfterValue": "200000",
@@ -393,6 +449,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@@ -400,6 +457,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@@ -407,6 +465,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@@ -414,6 +473,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@@ -421,6 +481,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@@ -428,6 +489,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -435,6 +497,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -442,6 +505,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -449,6 +513,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -456,6 +521,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -463,6 +529,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -470,6 +537,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -477,6 +545,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -484,6 +553,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -491,6 +561,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -498,6 +569,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@@ -505,6 +577,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@@ -512,6 +585,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@@ -519,6 +593,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@@ -526,6 +601,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@@ -533,6 +609,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -540,6 +617,7 @@
},
{
"BriefDescription": "L2 cache demand requests from this core that missed the L2",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -547,6 +625,7 @@
},
{
"BriefDescription": "L2 cache demand requests from this core",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -554,6 +633,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -561,6 +641,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -568,6 +649,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -575,6 +657,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -582,6 +665,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -589,6 +673,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -596,6 +681,7 @@
},
{
"BriefDescription": "L2 cache requests",
+ "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -603,6 +689,7 @@
},
{
"BriefDescription": "L2 store requests",
+ "Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.E_STATE",
"SampleAfterValue": "200000",
@@ -610,6 +697,7 @@
},
{
"BriefDescription": "L2 store requests",
+ "Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.I_STATE",
"SampleAfterValue": "200000",
@@ -617,6 +705,7 @@
},
{
"BriefDescription": "L2 store requests",
+ "Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.MESI",
"SampleAfterValue": "200000",
@@ -624,6 +713,7 @@
},
{
"BriefDescription": "L2 store requests",
+ "Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.M_STATE",
"SampleAfterValue": "200000",
@@ -631,6 +721,7 @@
},
{
"BriefDescription": "L2 store requests",
+ "Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.S_STATE",
"SampleAfterValue": "200000",
@@ -638,6 +729,7 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (precise event).",
+ "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"SampleAfterValue": "200000",
@@ -645,6 +737,7 @@
},
{
"BriefDescription": "Retired loads that miss the L2 cache",
+ "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"SampleAfterValue": "10000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/counter.json b/tools/perf/pmu-events/arch/x86/bonnell/counter.json
new file mode 100644
index 000000000000..eb89b55f31bd
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/counter.json
@@ -0,0 +1,7 @@
+[
+ {
+ "Unit": "core",
+ "CountersNumFixed": "4",
+ "CountersNumGeneric": "2"
+ }
+] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
index 18bf5ec47e72..d1bd5be95a15 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Floating point assists for retired operations.",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "FP_ASSIST.AR",
"SampleAfterValue": "10000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Floating point assists.",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "FP_ASSIST.S",
"SampleAfterValue": "10000",
@@ -15,12 +17,14 @@
},
{
"BriefDescription": "SIMD assists invoked.",
+ "Counter": "0,1",
"EventCode": "0xCD",
"EventName": "SIMD_ASSIST",
"SampleAfterValue": "100000"
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
+ "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
@@ -28,6 +32,7 @@
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+ "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
@@ -35,6 +40,7 @@
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
+ "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
@@ -42,12 +48,14 @@
},
{
"BriefDescription": "SIMD Instructions retired.",
+ "Counter": "0,1",
"EventCode": "0xCE",
"EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
+ "Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
@@ -55,6 +63,7 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+ "Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
@@ -62,6 +71,7 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
+ "Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
@@ -69,6 +79,7 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
+ "Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000",
@@ -76,12 +87,14 @@
},
{
"BriefDescription": "Saturated arithmetic instructions retired.",
+ "Counter": "0,1",
"EventCode": "0xCF",
"EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
+ "Counter": "0,1",
"EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000",
@@ -89,12 +102,14 @@
},
{
"BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
+ "Counter": "0,1",
"EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD micro-ops retired (excluding stores).",
+ "Counter": "0,1",
"EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.AR",
"PEBS": "2",
@@ -103,12 +118,14 @@
},
{
"BriefDescription": "SIMD micro-ops executed (excluding stores).",
+ "Counter": "0,1",
"EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD packed arithmetic micro-ops retired",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000",
@@ -116,6 +133,7 @@
},
{
"BriefDescription": "SIMD packed arithmetic micro-ops executed",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000",
@@ -123,6 +141,7 @@
},
{
"BriefDescription": "SIMD packed logical micro-ops retired",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000",
@@ -130,6 +149,7 @@
},
{
"BriefDescription": "SIMD packed logical micro-ops executed",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000",
@@ -137,6 +157,7 @@
},
{
"BriefDescription": "SIMD packed multiply micro-ops retired",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000",
@@ -144,6 +165,7 @@
},
{
"BriefDescription": "SIMD packed multiply micro-ops executed",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000",
@@ -151,6 +173,7 @@
},
{
"BriefDescription": "SIMD packed micro-ops retired",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000",
@@ -158,6 +181,7 @@
},
{
"BriefDescription": "SIMD packed micro-ops executed",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000",
@@ -165,6 +189,7 @@
},
{
"BriefDescription": "SIMD packed shift micro-ops retired",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000",
@@ -172,6 +197,7 @@
},
{
"BriefDescription": "SIMD packed shift micro-ops executed",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000",
@@ -179,6 +205,7 @@
},
{
"BriefDescription": "SIMD unpacked micro-ops retired",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000",
@@ -186,6 +213,7 @@
},
{
"BriefDescription": "SIMD unpacked micro-ops executed",
+ "Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000",
@@ -193,6 +221,7 @@
},
{
"BriefDescription": "Floating point computational micro-ops retired.",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
"PEBS": "2",
@@ -201,6 +230,7 @@
},
{
"BriefDescription": "Floating point computational micro-ops executed.",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.S",
"SampleAfterValue": "2000000",
@@ -208,6 +238,7 @@
},
{
"BriefDescription": "FXCH uops retired.",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
"PEBS": "2",
@@ -216,6 +247,7 @@
},
{
"BriefDescription": "FXCH uops executed.",
+ "Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
index 42284c02c11d..7657fd6d3a11 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "BACLEARS asserted.",
+ "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Cycles during which instruction fetches are stalled.",
+ "Counter": "0,1",
"EventCode": "0x86",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "Decode stall due to IQ full",
+ "Counter": "0,1",
"EventCode": "0x87",
"EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "Decode stall due to PFB empty",
+ "Counter": "0,1",
"EventCode": "0x87",
"EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "Instruction fetches.",
+ "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "Icache hit",
+ "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "Icache miss",
+ "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "All Instructions decoded",
+ "Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "CISC macro instructions decoded",
+ "Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "Non-CISC macro instructions decoded",
+ "Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
+ "Counter": "0,1",
"CounterMask": "1",
"EventCode": "0xA9",
"EventName": "UOPS.MS_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
index ac02dc2482c8..f8b45b6fb4d3 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Nonzero segbase 1 bubble",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Nonzero segbase load 1 bubble",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "Load splits",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "Load splits (At Retirement)",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "ld-op-st splits",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "Memory references that cross an 8-byte boundary.",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "Nonzero segbase store 1 bubble",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "Store splits",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "Store splits (Ar Retirement)",
+ "Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
@@ -78,6 +89,7 @@
},
{
"BriefDescription": "L1 hardware prefetch request",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "2000000",
@@ -85,6 +97,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
@@ -92,6 +105,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
@@ -99,6 +113,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
@@ -106,6 +121,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "200000",
@@ -113,6 +129,7 @@
},
{
"BriefDescription": "Any Software prefetch",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
@@ -120,6 +137,7 @@
},
{
"BriefDescription": "Any Software prefetch",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
@@ -127,6 +145,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+ "Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json
index 782594c8bda5..3a55c101fbf7 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/other.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Bus queue is empty.",
+ "Counter": "0,1",
"EventCode": "0x7D",
"EventName": "BUSQ_EMPTY.SELF",
"SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Number of Bus Not Ready signals asserted.",
+ "Counter": "0,1",
"EventCode": "0x61",
"EventName": "BUS_BNR_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -15,12 +17,14 @@
},
{
"BriefDescription": "Number of Bus Not Ready signals asserted.",
+ "Counter": "0,1",
"EventCode": "0x61",
"EventName": "BUS_BNR_DRV.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Bus cycles while processor receives data.",
+ "Counter": "0,1",
"EventCode": "0x64",
"EventName": "BUS_DATA_RCV.SELF",
"SampleAfterValue": "200000",
@@ -28,6 +32,7 @@
},
{
"BriefDescription": "Bus cycles when data is sent on the bus.",
+ "Counter": "0,1",
"EventCode": "0x62",
"EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -35,12 +40,14 @@
},
{
"BriefDescription": "Bus cycles when data is sent on the bus.",
+ "Counter": "0,1",
"EventCode": "0x62",
"EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "HITM signal asserted.",
+ "Counter": "0,1",
"EventCode": "0x7B",
"EventName": "BUS_HITM_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -48,12 +55,14 @@
},
{
"BriefDescription": "HITM signal asserted.",
+ "Counter": "0,1",
"EventCode": "0x7B",
"EventName": "BUS_HITM_DRV.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "HIT signal asserted.",
+ "Counter": "0,1",
"EventCode": "0x7A",
"EventName": "BUS_HIT_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -61,12 +70,14 @@
},
{
"BriefDescription": "HIT signal asserted.",
+ "Counter": "0,1",
"EventCode": "0x7A",
"EventName": "BUS_HIT_DRV.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "IO requests waiting in the bus queue.",
+ "Counter": "0,1",
"EventCode": "0x7F",
"EventName": "BUS_IO_WAIT.SELF",
"SampleAfterValue": "200000",
@@ -74,6 +85,7 @@
},
{
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -81,6 +93,7 @@
},
{
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "BUS_LOCK_CLOCKS.SELF",
"SampleAfterValue": "200000",
@@ -88,6 +101,7 @@
},
{
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
+ "Counter": "0,1",
"EventCode": "0x60",
"EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -95,6 +109,7 @@
},
{
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
+ "Counter": "0,1",
"EventCode": "0x60",
"EventName": "BUS_REQUEST_OUTSTANDING.SELF",
"SampleAfterValue": "200000",
@@ -102,6 +117,7 @@
},
{
"BriefDescription": "All bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x70",
"EventName": "BUS_TRANS_ANY.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -109,6 +125,7 @@
},
{
"BriefDescription": "All bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x70",
"EventName": "BUS_TRANS_ANY.SELF",
"SampleAfterValue": "200000",
@@ -116,6 +133,7 @@
},
{
"BriefDescription": "Burst read bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x65",
"EventName": "BUS_TRANS_BRD.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -123,6 +141,7 @@
},
{
"BriefDescription": "Burst read bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x65",
"EventName": "BUS_TRANS_BRD.SELF",
"SampleAfterValue": "200000",
@@ -130,6 +149,7 @@
},
{
"BriefDescription": "Burst (full cache-line) bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6E",
"EventName": "BUS_TRANS_BURST.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -137,6 +157,7 @@
},
{
"BriefDescription": "Burst (full cache-line) bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6E",
"EventName": "BUS_TRANS_BURST.SELF",
"SampleAfterValue": "200000",
@@ -144,6 +165,7 @@
},
{
"BriefDescription": "Deferred bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6D",
"EventName": "BUS_TRANS_DEF.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -151,6 +173,7 @@
},
{
"BriefDescription": "Deferred bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6D",
"EventName": "BUS_TRANS_DEF.SELF",
"SampleAfterValue": "200000",
@@ -158,6 +181,7 @@
},
{
"BriefDescription": "Instruction-fetch bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x68",
"EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -165,6 +189,7 @@
},
{
"BriefDescription": "Instruction-fetch bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x68",
"EventName": "BUS_TRANS_IFETCH.SELF",
"SampleAfterValue": "200000",
@@ -172,6 +197,7 @@
},
{
"BriefDescription": "Invalidate bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x69",
"EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -179,6 +205,7 @@
},
{
"BriefDescription": "Invalidate bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x69",
"EventName": "BUS_TRANS_INVAL.SELF",
"SampleAfterValue": "200000",
@@ -186,6 +213,7 @@
},
{
"BriefDescription": "IO bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -193,6 +221,7 @@
},
{
"BriefDescription": "IO bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.SELF",
"SampleAfterValue": "200000",
@@ -200,6 +229,7 @@
},
{
"BriefDescription": "Memory bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6F",
"EventName": "BUS_TRANS_MEM.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -207,6 +237,7 @@
},
{
"BriefDescription": "Memory bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6F",
"EventName": "BUS_TRANS_MEM.SELF",
"SampleAfterValue": "200000",
@@ -214,6 +245,7 @@
},
{
"BriefDescription": "Partial bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6B",
"EventName": "BUS_TRANS_P.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -221,6 +253,7 @@
},
{
"BriefDescription": "Partial bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x6B",
"EventName": "BUS_TRANS_P.SELF",
"SampleAfterValue": "200000",
@@ -228,6 +261,7 @@
},
{
"BriefDescription": "Partial write bus transaction.",
+ "Counter": "0,1",
"EventCode": "0x6A",
"EventName": "BUS_TRANS_PWR.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -235,6 +269,7 @@
},
{
"BriefDescription": "Partial write bus transaction.",
+ "Counter": "0,1",
"EventCode": "0x6A",
"EventName": "BUS_TRANS_PWR.SELF",
"SampleAfterValue": "200000",
@@ -242,6 +277,7 @@
},
{
"BriefDescription": "RFO bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x66",
"EventName": "BUS_TRANS_RFO.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -249,6 +285,7 @@
},
{
"BriefDescription": "RFO bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x66",
"EventName": "BUS_TRANS_RFO.SELF",
"SampleAfterValue": "200000",
@@ -256,6 +293,7 @@
},
{
"BriefDescription": "Explicit writeback bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x67",
"EventName": "BUS_TRANS_WB.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -263,6 +301,7 @@
},
{
"BriefDescription": "Explicit writeback bus transactions.",
+ "Counter": "0,1",
"EventCode": "0x67",
"EventName": "BUS_TRANS_WB.SELF",
"SampleAfterValue": "200000",
@@ -270,6 +309,7 @@
},
{
"BriefDescription": "Cycles during which interrupts are disabled.",
+ "Counter": "0,1",
"EventCode": "0xC6",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
"SampleAfterValue": "2000000",
@@ -277,6 +317,7 @@
},
{
"BriefDescription": "Cycles during which interrupts are pending and disabled.",
+ "Counter": "0,1",
"EventCode": "0xC6",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
"SampleAfterValue": "2000000",
@@ -284,6 +325,7 @@
},
{
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
+ "Counter": "0,1",
"EventCode": "0x9",
"EventName": "DISPATCH_BLOCKED.ANY",
"SampleAfterValue": "200000",
@@ -291,12 +333,14 @@
},
{
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
+ "Counter": "0,1",
"EventCode": "0x3A",
"EventName": "EIST_TRANS",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
"SampleAfterValue": "200000",
@@ -304,6 +348,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
"SampleAfterValue": "200000",
@@ -311,6 +356,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
"SampleAfterValue": "200000",
@@ -318,6 +364,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
"SampleAfterValue": "200000",
@@ -325,6 +372,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.ANY",
"SampleAfterValue": "200000",
@@ -332,6 +380,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
"SampleAfterValue": "200000",
@@ -339,6 +388,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.HIT",
"SampleAfterValue": "200000",
@@ -346,6 +396,7 @@
},
{
"BriefDescription": "External snoops.",
+ "Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.HITM",
"SampleAfterValue": "200000",
@@ -353,12 +404,14 @@
},
{
"BriefDescription": "Hardware interrupts received.",
+ "Counter": "0,1",
"EventCode": "0xC8",
"EventName": "HW_INT_RCV",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Number of segment register loads.",
+ "Counter": "0,1",
"EventCode": "0x6",
"EventName": "SEGMENT_REG_LOADS.ANY",
"SampleAfterValue": "200000",
@@ -366,6 +419,7 @@
},
{
"BriefDescription": "Bus stalled for snoops.",
+ "Counter": "0,1",
"EventCode": "0x7E",
"EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@@ -373,6 +427,7 @@
},
{
"BriefDescription": "Bus stalled for snoops.",
+ "Counter": "0,1",
"EventCode": "0x7E",
"EventName": "SNOOP_STALL_DRV.SELF",
"SampleAfterValue": "200000",
@@ -380,6 +435,7 @@
},
{
"BriefDescription": "Number of thermal trips",
+ "Counter": "0,1",
"EventCode": "0x3B",
"EventName": "THERMAL_TRIP",
"SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
index 91b98ee8ba9a..9ff032ab11e2 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Bogus branches",
+ "Counter": "0,1",
"EventCode": "0xE4",
"EventName": "BOGUS_BR",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Branch instructions decoded",
+ "Counter": "0,1",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@@ -15,12 +17,14 @@
},
{
"BriefDescription": "Retired branch instructions.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Retired branch instructions.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ANY1",
"SampleAfterValue": "2000000",
@@ -28,6 +32,7 @@
},
{
"BriefDescription": "Retired mispredicted branch instructions (precise event).",
+ "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_INST_RETIRED.MISPRED",
"PEBS": "1",
@@ -35,6 +40,7 @@
},
{
"BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
"SampleAfterValue": "200000",
@@ -42,6 +48,7 @@
},
{
"BriefDescription": "Retired branch instructions that were mispredicted taken.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
"SampleAfterValue": "200000",
@@ -49,6 +56,7 @@
},
{
"BriefDescription": "Retired branch instructions that were predicted not-taken.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
"SampleAfterValue": "2000000",
@@ -56,6 +64,7 @@
},
{
"BriefDescription": "Retired branch instructions that were predicted taken.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.PRED_TAKEN",
"SampleAfterValue": "2000000",
@@ -63,6 +72,7 @@
},
{
"BriefDescription": "Retired taken branch instructions.",
+ "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "2000000",
@@ -70,6 +80,7 @@
},
{
"BriefDescription": "All macro conditional branch instructions.",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND",
"SampleAfterValue": "2000000",
@@ -77,6 +88,7 @@
},
{
"BriefDescription": "Only taken macro conditional branch instructions",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "2000000",
@@ -84,6 +96,7 @@
},
{
"BriefDescription": "All non-indirect calls",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
"SampleAfterValue": "2000000",
@@ -91,6 +104,7 @@
},
{
"BriefDescription": "All indirect branches that are not calls.",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.IND",
"SampleAfterValue": "2000000",
@@ -98,6 +112,7 @@
},
{
"BriefDescription": "All indirect calls, including both register and memory indirect.",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "2000000",
@@ -105,6 +120,7 @@
},
{
"BriefDescription": "All indirect branches that have a return mnemonic",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.RET",
"SampleAfterValue": "2000000",
@@ -112,6 +128,7 @@
},
{
"BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
+ "Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.UNCOND",
"SampleAfterValue": "2000000",
@@ -119,6 +136,7 @@
},
{
"BriefDescription": "Mispredicted cond branch instructions retired",
+ "Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
"SampleAfterValue": "200000",
@@ -126,6 +144,7 @@
},
{
"BriefDescription": "Mispredicted and taken cond branch instructions retired",
+ "Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "200000",
@@ -133,6 +152,7 @@
},
{
"BriefDescription": "Mispredicted ind branches that are not calls",
+ "Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND",
"SampleAfterValue": "200000",
@@ -140,6 +160,7 @@
},
{
"BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
+ "Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "200000",
@@ -147,6 +168,7 @@
},
{
"BriefDescription": "Mispredicted return branches",
+ "Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
"SampleAfterValue": "200000",
@@ -154,6 +176,7 @@
},
{
"BriefDescription": "Bus cycles when core is not halted",
+ "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.BUS",
"SampleAfterValue": "200000",
@@ -161,24 +184,28 @@
},
{
"BriefDescription": "Core cycles when core is not halted",
+ "Counter": "Fixed counter 2",
"EventCode": "0xA",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Core cycles when core is not halted",
+ "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference cycles when core is not halted.",
+ "Counter": "Fixed counter 3",
"EventCode": "0xA",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles the divider is busy.",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -186,6 +213,7 @@
},
{
"BriefDescription": "Divide operations retired",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "DIV.AR",
"SampleAfterValue": "2000000",
@@ -193,6 +221,7 @@
},
{
"BriefDescription": "Divide operations executed.",
+ "Counter": "0,1",
"EventCode": "0x13",
"EventName": "DIV.S",
"SampleAfterValue": "2000000",
@@ -200,12 +229,14 @@
},
{
"BriefDescription": "Instructions retired.",
+ "Counter": "Fixed counter 1",
"EventCode": "0xA",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (precise event).",
+ "Counter": "0,1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "2",
@@ -213,6 +244,7 @@
},
{
"BriefDescription": "Self-Modifying Code detected.",
+ "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200000",
@@ -220,6 +252,7 @@
},
{
"BriefDescription": "Multiply operations retired",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "MUL.AR",
"SampleAfterValue": "2000000",
@@ -227,6 +260,7 @@
},
{
"BriefDescription": "Multiply operations executed.",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "MUL.S",
"SampleAfterValue": "2000000",
@@ -234,6 +268,7 @@
},
{
"BriefDescription": "Micro-op reissues for any cause",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.ANY",
"SampleAfterValue": "200000",
@@ -241,6 +276,7 @@
},
{
"BriefDescription": "Micro-op reissues for any cause (At Retirement)",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.ANY.AR",
"SampleAfterValue": "200000",
@@ -248,6 +284,7 @@
},
{
"BriefDescription": "Micro-op reissues on a store-load collision",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.OVERLAP_STORE",
"SampleAfterValue": "200000",
@@ -255,6 +292,7 @@
},
{
"BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
+ "Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.OVERLAP_STORE.AR",
"SampleAfterValue": "200000",
@@ -262,6 +300,7 @@
},
{
"BriefDescription": "Cycles issue is stalled due to div busy.",
+ "Counter": "0,1",
"EventCode": "0xDC",
"EventName": "RESOURCE_STALLS.DIV_BUSY",
"SampleAfterValue": "2000000",
@@ -269,6 +308,7 @@
},
{
"BriefDescription": "All store forwards",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "STORE_FORWARDS.ANY",
"SampleAfterValue": "200000",
@@ -276,6 +316,7 @@
},
{
"BriefDescription": "Good store forwards",
+ "Counter": "0,1",
"EventCode": "0x2",
"EventName": "STORE_FORWARDS.GOOD",
"SampleAfterValue": "200000",
@@ -283,6 +324,7 @@
},
{
"BriefDescription": "Micro-ops retired.",
+ "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"SampleAfterValue": "2000000",
@@ -290,6 +332,7 @@
},
{
"BriefDescription": "Cycles no micro-ops retired.",
+ "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALLED_CYCLES",
"SampleAfterValue": "2000000",
@@ -297,6 +340,7 @@
},
{
"BriefDescription": "Periods no micro-ops retired.",
+ "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALLS",
"SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
index 82e07c73cff0..e8512c585572 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Memory accesses that missed the DTLB.",
+ "Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "DTLB misses due to load operations.",
+ "Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "DTLB misses due to store operations.",
+ "Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "L0 DTLB misses due to load operations.",
+ "Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "L0 DTLB misses due to store operations",
+ "Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "ITLB flushes.",
+ "Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "ITLB hits.",
+ "Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.HIT",
"SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "ITLB misses.",
+ "Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.MISSES",
"PEBS": "2",
@@ -58,6 +66,7 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (precise event).",
+ "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@@ -66,6 +75,7 @@
},
{
"BriefDescription": "Duration of page-walks in core cycles",
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "2000000",
@@ -73,6 +83,7 @@
},
{
"BriefDescription": "Duration of D-side only page walks",
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000",
@@ -80,6 +91,7 @@
},
{
"BriefDescription": "Number of D-side only page walks",
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000",
@@ -87,6 +99,7 @@
},
{
"BriefDescription": "Duration of I-Side page walks",
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "2000000",
@@ -94,6 +107,7 @@
},
{
"BriefDescription": "Number of I-Side page walks",
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000",
@@ -101,6 +115,7 @@
},
{
"BriefDescription": "Number of page-walks executed.",
+ "Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000",
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