diff options
| author | Ian Rogers <irogers@google.com> | 2022-12-14 22:54:58 -0800 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-12-21 14:52:41 -0300 |
| commit | 5362e4d1f24ed4d4edd9dc1cbf846218c88eabc3 (patch) | |
| tree | dcc8411f7f73e576e48e605ba4004210135d43a7 /tools/perf/pmu-events/arch/x86/meteorlake/frontend.json | |
| parent | 2c3fd22bb3ff166a072c083e6b7468259c37e46a (diff) | |
perf vendor events intel: Refresh meteorlake events
Update the meteorlake events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but they are sorted and unused json values
are removed. This increases consistency across the json files. The
CPUID matching regular expression is updated to match the perfmon one.
Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-12-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/meteorlake/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/meteorlake/frontend.json | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json index 9657768fc95a..7de11819dd0d 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json @@ -1,22 +1,16 @@ [ { "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", - "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", "UMask": "0x3", "Unit": "cpu_atom" }, { "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.MISSES", - "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", "UMask": "0x2", "Unit": "cpu_atom" |