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| author | Russell King <[email protected]> | 2015-07-09 00:30:24 +0100 |
|---|---|---|
| committer | Russell King <[email protected]> | 2015-07-17 15:08:40 +0100 |
| commit | bac51ad9d14f6baed3730ef53bedc1eb2238563a (patch) | |
| tree | 5e7b392f695b499cbb257caba47caac36a0fb963 /tools/perf/builtin-diff.c | |
| parent | 462859aa7bbe1ac83ec4377a0a06fe60778f3f27 (diff) | |
ARM: invalidate L1 before enabling coherency
We must invalidate the L1 cache before enabling coherency, otherwise
secondary CPUs can inject invalid cache lines into the coherent CPU
cluster, which could then be migrated to other CPUs. This fixes a
recent regression with SoCFPGA randomly failing to boot.
Fixes: 02b4e2756e01 ("ARM: v7 setup function should invalidate L1 cache")
Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/builtin-diff.c')
0 files changed, 0 insertions, 0 deletions