diff options
| author | Vijendar Mukunda <Vijendar.Mukunda@amd.com> | 2022-02-23 12:49:31 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-02-24 02:04:26 +0000 |
| commit | 5ca4cf2c83dac27768f1d7d3e2404f5a17830ca5 (patch) | |
| tree | a28ca680a1a699f8adbdb90981f40539de748201 /sound/soc/amd/vangogh/acp5x.h | |
| parent | 4b0bec6088588a120d33db85b1f0d9f096d1df71 (diff) | |
ASoC: amd: vangogh: refactor i2s master mode clock sequence code
Refactor I2S Master mode clock programming sequence code.
This will also fix the i2s clocks restore issue during system level
resume.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20220223071959.13539-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/amd/vangogh/acp5x.h')
| -rw-r--r-- | sound/soc/amd/vangogh/acp5x.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h index fe5e1fa98974..b85d3ee369a3 100644 --- a/sound/soc/amd/vangogh/acp5x.h +++ b/sound/soc/amd/vangogh/acp5x.h @@ -105,6 +105,8 @@ struct i2s_stream_instance { dma_addr_t dma_addr; u64 bytescount; void __iomem *acp5x_base; + u32 lrclk_div; + u32 bclk_div; }; union acp_dma_count { @@ -191,3 +193,30 @@ static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd, } return byte_count.bytescount; } + +static inline void acp5x_set_i2s_clk(struct i2s_dev_data *adata, + struct i2s_stream_instance *rtd) +{ + union acp_i2stdm_mstrclkgen mclkgen; + u32 master_reg; + + switch (rtd->i2s_instance) { + case I2S_HS_INSTANCE: + master_reg = ACP_I2STDM2_MSTRCLKGEN; + break; + case I2S_SP_INSTANCE: + default: + master_reg = ACP_I2STDM0_MSTRCLKGEN; + break; + } + + mclkgen.bits.i2stdm_master_mode = 0x1; + if (adata->tdm_mode) + mclkgen.bits.i2stdm_format_mode = 0x01; + else + mclkgen.bits.i2stdm_format_mode = 0x00; + + mclkgen.bits.i2stdm_bclk_div_val = rtd->bclk_div; + mclkgen.bits.i2stdm_lrclk_div_val = rtd->lrclk_div; + acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg); +} |