diff options
| author | Dave Ertman <david.m.ertman@intel.com> | 2023-01-27 14:24:10 +0100 |
|---|---|---|
| committer | Tony Nguyen <anthony.l.nguyen@intel.com> | 2023-03-07 13:02:01 -0800 |
| commit | fef3f92e8a4214652d8f33f50330dc5a92efbf11 (patch) | |
| tree | 1acdfee502c393091d51e1b6b7572cacefb4b565 /sound/isa | |
| parent | 382e363d5bed0cec5807b35761d14e55955eee63 (diff) | |
ice: Fix DSCP PFC TLV creation
When creating the TLV to send to the FW for configuring DSCP mode PFC,the
PFCENABLE field was being masked with a 4 bit mask (0xF), but this is an 8
bit bitmask for enabled classes for PFC. This means that traffic classes
4-7 could not be enabled for PFC.
Remove the mask completely, as it is not necessary, as we are assigning 8
bits to an 8 bit field.
Fixes: 2a87bd73e50d ("ice: Add DSCP support")
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
Tested-by: Gurucharan G <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Diffstat (limited to 'sound/isa')
0 files changed, 0 insertions, 0 deletions