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authorSergio Paracuellos <[email protected]>2021-06-14 12:06:16 +0200
committerGreg Kroah-Hartman <[email protected]>2021-06-15 15:24:29 +0200
commitb15606e63ea90ced5044bd2007fd7b54298ce293 (patch)
treeb1195c7f4276205e5e5d359332cd0a4ee8730849 /scripts/tracing/draw_functrace.py
parent222b27713d7f7e189cca30ccdcee8e1f953d2c9f (diff)
staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges'
After 'PCI_IOBASE' is defined for ralink, ranges are properly parsed using pci generic APIS and there is no need to parse anything manually. So function 'mt7621_pci_parse_request_of_pci_ranges' used for this can be enterely removed. Since we have to configure iocu memory regions and pci io windows resources must be retrieved accordly from 'bridge->windows' but there is no need to store anything as driver private data. Signed-off-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'scripts/tracing/draw_functrace.py')
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