diff options
| author | Vignesh Raghavendra <[email protected]> | 2021-03-04 23:10:35 +0200 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2021-03-09 08:46:41 -0600 |
| commit | 3753b12877b62bea3bed44431ad0cf6906cb3fdf (patch) | |
| tree | a42d47d30685196a576e9aa812c62c96c053b463 /scripts/stackusage | |
| parent | b605d4f66f5149168bd9e8317ddc9f6b9bdaa1df (diff) | |
arm64: dts: ti: k3-am64-main: Add CPSW DT node
Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
feature), so that CPSW DMA channel participates in Coherency and thus avoid
need to cache maintenance for SKBs. This improves bidirectional TCP
performance by up to 100Mbps (on 1G link).
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Grygorii Strashko <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'scripts/stackusage')
0 files changed, 0 insertions, 0 deletions