clk: imx7d: create clocks behind rawnand clock gate

The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.

Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.

Signed-off-by: Stefan Agner <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Acked-by: Han Xu <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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