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| author | Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> | 2022-11-10 17:19:12 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2022-11-23 11:46:31 -0500 |
| commit | 71b6b2557058d4374d11e792ec550a1a098fb7a9 (patch) | |
| tree | 0ab4c050108db2b02e7cd1ca1786a707fb394053 /scripts/generate_rust_target.rs | |
| parent | dfa5e6ef3ccefff9fa8a70d9f5fa6ef6244aa312 (diff) | |
i915/uncore: Acquire fw before loop in intel_uncore_read64_2x32
PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
32 bit registers are read in a loop, there is a latency involved between
getting the GT timestamp and the CPU timestamp. As part of the
resolution, refactor intel_uncore_read64_2x32 to acquire forcewake and
uncore lock prior to reading upper and lower regs.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221110171913.670286-2-umesh.nerlige.ramappa@intel.com
(cherry picked from commit e746f84b8e813816951b63485134927ed6763a1b)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'scripts/generate_rust_target.rs')
0 files changed, 0 insertions, 0 deletions