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| author | Shenwei Wang <[email protected]> | 2023-04-10 14:55:55 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2023-04-20 13:42:30 +0200 |
| commit | f73fd750552524b06b5d77ebfdd106ccc8fcac61 (patch) | |
| tree | 3737eb93dffc0e1f1d471935d61cd6e583dde199 /scripts/generate_rust_analyzer.py | |
| parent | 9e4f2a8004213339e9d837d891a59cc80e082966 (diff) | |
tty: serial: fsl_lpuart: adjust buffer length to the intended size
Based on the fls function definition provided below, we should not
subtract 1 to obtain the correct buffer length:
fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
Fixes: 5887ad43ee02 ("tty: serial: fsl_lpuart: Use cyclic DMA for Rx")
Signed-off-by: Shenwei Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions