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authorJan Kuliga <[email protected]>2023-12-18 12:39:38 +0100
committerVinod Koul <[email protected]>2023-12-21 21:51:54 +0530
commite5bc76b0e1c54906ca744ed1a7872f4f407d5d2e (patch)
tree35a98c5f4050c2f7d71a3158b37baa38cfe32810 /scripts/generate_rust_analyzer.py
parent7a9c7f46bd0abea214d96f00f78622f24c798ad8 (diff)
dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
According to the XDMA datasheet (PG195), the address of any descriptor must be 32 byte aligned. The datasheet also states that a contiguous block of descriptors must not cross a 4k address boundary. Therefore, it is possible to ease the pressure put on the dma_pool allocator just by requiring sufficient alignment and boundary values. Add proper macro definition and change the values passed into the dma_pool_create(). Signed-off-by: Jan Kuliga <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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