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authorPalmer Dabbelt <[email protected]>2023-06-19 10:21:01 -0700
committerPalmer Dabbelt <[email protected]>2023-07-01 07:38:18 -0700
commite50db34efdc8cac2f17b8f5d32fddd7b58914ce6 (patch)
tree9dda50236d992a17e0c337e9249998a871420c66 /scripts/generate_rust_analyzer.py
parentbcc8790057c1f02d20654f68d107973405c1f823 (diff)
RISC-V: Fix up some vector state related build failures
I get a few build failures along the lines of ./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type 19 | struct __riscv_v_ext_state v_state; | ^~~~~~~ ./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type 32 | struct __riscv_extra_ext_header sc_extdesc; The V structures in question are defined for !assembly, so let's just do so for the others. Fixes: 8ee0b41898fa ("riscv: signal: Add sigcontext save/restore for vector") Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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