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author | Jim Quinlan <[email protected]> | 2024-08-15 18:57:22 -0400 |
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committer | Krzysztof Wilczyński <[email protected]> | 2024-09-04 13:59:28 +0000 |
commit | e1c88956e200e225f2712de4b5e2be923cf559fc (patch) | |
tree | c7e4a8b896dc725afc59dee4e5de653fe02f3b53 /scripts/generate_rust_analyzer.py | |
parent | 0d8046037610dcf9e59ece73bf4bbcec1e6a878b (diff) |
PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl
Add a "has_phy" field indicating that the internal PHY has SW control
that requires configuration. Some previous chips only required the
firing of the "rescal" reset controller.
This change requires us to give the 7216 SoC its own cfg_data structure.
Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Tested-by: Florian Fainelli <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Stanimir Varbanov <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions