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authorManivannan Sadhasivam <[email protected]>2023-03-08 13:54:17 +0530
committerBjorn Andersson <[email protected]>2023-03-15 19:38:50 -0700
commitc9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3 (patch)
tree38217719697268719c179f63b9450bf96a77d6a6 /scripts/generate_rust_analyzer.py
parent3b76b736cd9933ff88764ffec01cbd859c1475e7 (diff)
ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}
There is only one PCIe PHY in this SoC, so there is no need to add an index to the suffix. This also matches the naming convention of the PCIe controller. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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