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authorJai Luthra <[email protected]>2024-06-11 18:02:56 +0530
committerMark Brown <[email protected]>2024-06-11 17:13:32 +0100
commitc5dcf8ab10606e76c1d8a0ec77f27d84a392e874 (patch)
treee9ddb900f620733cff89567badec1e24e731cc64 /scripts/generate_rust_analyzer.py
parente8343410ddf08fc36a9b9cc7c51a4e53a262d4c6 (diff)
ASoC: ti: davinci-mcasp: Set min period size using FIFO config
The minimum period size was enforced to 64 as older devices integrating McASP with EDMA used an internal FIFO of 64 samples. With UDMA based platforms this internal McASP FIFO is optional, as the DMA engine internally does some buffering which is already accounted for when registering the platform. So we should read the actual FIFO configuration (txnumevt/rxnumevt) instead of hardcoding frames.min to 64. Acked-by: Peter Ujfalusi <[email protected]> Signed-off-by: Jai Luthra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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