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| author | Claudiu Beznea <[email protected]> | 2023-09-29 08:38:51 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2023-10-05 13:45:16 +0200 |
| commit | bf51d3b2d048c312764a55d91d67a85ee5535e31 (patch) | |
| tree | ab610c3377324ad403ac666c300584dddfedb61c /scripts/generate_rust_analyzer.py | |
| parent | d2692ed490e680a41401cef879adebcfafb4298f (diff) | |
clk: renesas: rzg2l: Trust value returned by hardware
The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The
hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that
setting 0 is prohibited. Hence rzg2l_cpg_sd_clk_mux_get_parent() should
just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock
parent index based on the value read.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions