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author | Conor Dooley <[email protected]> | 2022-12-05 17:45:00 +0000 |
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committer | Palmer Dabbelt <[email protected]> | 2023-01-06 10:31:09 -0800 |
commit | a943385aa80151c6b2611d3a1cf8338af2b257a1 (patch) | |
tree | 4a21a148fca4427b01963b1896bf8c3655798216 /scripts/generate_rust_analyzer.py | |
parent | ec64efc4966edf19fa1bc398a26bddfbadc1605f (diff) |
dt-bindings: riscv: fix single letter canonical order
I used the wikipedia table for ordering extensions when updating the
pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new
riscv,isa strings for emulators").
Unfortunately that table did not match canonical order, as defined by
the RISC-V ISA Manual, which defines extension ordering in (what is
currently) Table 41, "Standard ISA extension names". Fix things up by
re-sorting v (vector) and adding p (packed-simd) & j (dynamic
languages). The e (reduced integer) and g (general) extensions are still
intentionally left out.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions