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| author | Krzysztof Kozlowski <[email protected]> | 2024-08-18 19:28:43 +0200 |
|---|---|---|
| committer | Krzysztof Wilczyński <[email protected]> | 2024-09-04 14:32:34 +0000 |
| commit | a5c1bf7e9a4638fbb27461e9801f07204b50dcb6 (patch) | |
| tree | 070abd3e6d11e356630d4b0256c96b6bb227c83f /scripts/generate_rust_analyzer.py | |
| parent | c62a0b8fe8bfbaa78efe5de7b30a9d0d225be1ab (diff) | |
dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".
Add missing top-level constraints for clock-names and reset-names.
Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Kunihiko Hayashi <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions