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| author | Miquel Raynal <[email protected]> | 2023-07-14 03:37:54 +0200 |
|---|---|---|
| committer | Neil Armstrong <[email protected]> | 2023-08-01 10:29:59 +0200 |
| commit | a368b40836e7fc4f24dbb0fcfb9dedcde1dcaa38 (patch) | |
| tree | 895c0ad20891390cd29e3a94cd249452f915279f /scripts/generate_rust_analyzer.py | |
| parent | 6b00e72e4bee08048379a6365251b195b8a946d1 (diff) | |
drm/panel: sitronix-st7789v: Clarify a definition
The Sitronix datasheet explains BIT(1) of the RGBCTRL register as the
DOTCLK/PCLK edge used to sample the data lines:
“0” The data is input on the positive edge of DOTCLK
“1” The data is input on the negative edge of DOTCLK
IOW, this bit implies a falling edge and not a high state. Correct the
definition to ease the comparison with the datasheet.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Tested-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions