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authorPeter Griffin <[email protected]>2024-04-26 13:20:03 +0100
committerMartin K. Petersen <[email protected]>2024-05-06 21:34:37 -0400
commit6f9f0d564b0411f8d86d73c7cb6b2703839e8a96 (patch)
treeb9869429cd76f5a13409413fd11b6d8f82deb0a9 /scripts/generate_rust_analyzer.py
parentc9deb9a4f574b49bfd00be88aba470659d2db671 (diff)
scsi: ufs: exynos: Add some pa_dbg_ register offsets into drvdata
This allows these registers to be at different offsets or not exist at all on some SoCs variants. Signed-off-by: Peter Griffin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Krzysztof Kozlowski <[email protected]> Tested-by: Will McVicker <[email protected]> Signed-off-by: Martin K. Petersen <[email protected]>
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