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| author | Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> | 2024-08-05 19:17:04 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-08-07 18:23:59 -0400 |
| commit | 6ad9dafba19f15a64f71c2e1a9e3b6932f96628e (patch) | |
| tree | 2eafe61184fb2ef2d96e90ba6f543e0636a4e9e2 /scripts/generate_rust_analyzer.py | |
| parent | 7fc5f252c0d21b7b89720386344b614733edab32 (diff) | |
drm/amdgpu: Add DCC GFX12 flag to enable address alignment
We require this flag AMDGPU_GEM_CREATE_GFX12_DCC or any other
kernel level GFX12 DCC flag to differentiate the DCC buffers and other
pinned display buffers(which has TTM_PL_FLAG_CONTIGUOUS enabled).
If we use the TTM_PL_FLAG_CONTIGUOUS flag for DCC buffers, we may over
allocate for all the pinned display buffers unnecessarily that leads to
memory allocation failure.
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 46142cc1b9272d664e0258e105b537735bfeeccc)
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions