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author | Mark Brown <[email protected]> | 2023-10-23 18:19:12 +0100 |
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committer | Mark Brown <[email protected]> | 2023-10-26 14:00:42 +0100 |
commit | 6a2e332c2cbddd17d7dcb8f334953593f1324c8e (patch) | |
tree | 4c6a64e0ca03caafe774a36a41888825281671c2 /scripts/generate_rust_analyzer.py | |
parent | fabe32cc1eca7857837abcb56b242bc4845b7067 (diff) |
regmap: kunit: Add test for cache sync interaction with ranges
Hector Martin reports that since when doing a cache sync we enable cache
bypass if the selector register for a range is cached then we might leave
the physical selector register pointing to a different value to that which
we have in the cache. If we then try to write to the page that our cache
tells us is selected we will not update the selector register and write to
the wrong page. Add a test case covering this.
Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions