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authorAndy Chiu <[email protected]>2023-06-27 01:55:55 +0000
committerPalmer Dabbelt <[email protected]>2023-07-01 07:38:22 -0700
commit5c93c4c72fbc69f0f1cdf43c9402b923314e67c8 (patch)
treedba54ed4062320b45b8c700593cc09325ee9aa32 /scripts/generate_rust_analyzer.py
parent75b59f2a90aa7ccac62e3dcb680dfb967b341431 (diff)
selftests: Test RISC-V Vector's first-use handler
This add a test to check if the kernel zero-initializes all V registers after the first-use trap handler returns. If V registers are not zero-initialized, then the test should fail one out of several runs: ``` root@sifive-fpga:~# ./v_initval_nolibc # vl = 256 not ok 1 detect stale values on v-regesters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4c 41 4e 47 3d 43 0 50 41 54 48 3d 2f 75 73 72 2f 6c 6f 63 61 6c 2f 73 62 69 6e 3a 2f 75 73 72 2f 6c 6f 63 61 6c 2f 62 69 6e 3a 2f 75 73 72 ff ff 81 0 0 0 0 0 0 0 0 0 0 0 0 0 ``` Otherwise, the test passes without errors each run. Signed-off-by: Andy Chiu <[email protected]> Reviewed-by: Björn Töpel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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