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author | Peng Fan <[email protected]> | 2023-04-03 17:52:56 +0800 |
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committer | Abel Vesa <[email protected]> | 2023-04-09 16:48:54 +0300 |
commit | 56b8d0bf3ea8b0db8543e04a6b97348a543405ab (patch) | |
tree | 4f2d14f0206602d823192ed13fc107a02a4d9d1d /scripts/generate_rust_analyzer.py | |
parent | 4435467b15b069e5a6f50ca9a9260e86b74dbc13 (diff) |
clk: imx: fracn-gppll: support integer pll
The fracn gppll could be configured in FRAC or INTEGER mode during
hardware design. The current driver only support FRAC mode, while
this patch introduces INTEGER support. When the PLL is INTEGER pll,
there is no mfn, mfd, the calculation is as below:
Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI]
Fclko_odiv = Fvco_clk / DIV[ODIV]
In this patch, we reuse the FRAC pll logic with some condition check to
simplify the driver
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions