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| author | Mark Brown <[email protected]> | 2023-06-20 15:23:56 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2023-06-20 15:23:56 +0100 |
| commit | 29735f6fb0f57c8010c9486216361c0f68c90226 (patch) | |
| tree | bc92a9989002250a49c25ed6f65b11bd6eb19058 /scripts/generate_rust_analyzer.py | |
| parent | 246c9f586c7c840b88efc874c949706d3f7df30c (diff) | |
| parent | 9321015a5f40891e7cb094c6f68f6d4f67b5f3dc (diff) | |
ASoC: Use maple tree register cache for Everest Semi
Merge series from Mark Brown <[email protected]>:
Several of the Everest Semi CODECs only support single register read and
write operations and therefore do not benefit from using the rbtree
cache over the maple tree cache, convert them to the more modern maple
tree cache.
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions