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author | Aurabindo Pillai <[email protected]> | 2024-10-01 18:03:02 -0400 |
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committer | Alex Deucher <[email protected]> | 2024-10-22 18:10:55 -0400 |
commit | 23d16ede33a4db4973468bf6652a09da5efd1468 (patch) | |
tree | 3fccc86481acb34dcde53878eab0a3187946abe0 /scripts/generate_rust_analyzer.py | |
parent | f67644b219d458d4b314e78f2304b73985390311 (diff) |
drm/amd/display: temp w/a for dGPU to enter idle optimizations
[Why&How]
vblank immediate disable currently does not work for all asics. On
DCN401, the vblank interrupts never stop coming, and hence we never
get a chance to trigger idle optimizations.
Add a workaround to enable immediate disable only on APUs for now. This
adds a 2-frame delay for triggering idle optimization, which is a
negligible overhead.
Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for older ASICs")
Fixes: e45b6716de4b ("drm/amd/display: use a more lax vblank enable policy for DCN35+")
Cc: Mario Limonciello <[email protected]>
Cc: Alex Deucher <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Aurabindo Pillai <[email protected]>
Signed-off-by: Wayne Lin <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
(cherry picked from commit 9b47278cec98e9894adf39229e91aaf4ab9140c5)
Cc: [email protected]
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions