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authorCiprian Regus <[email protected]>2024-02-23 18:21:27 +0200
committerPaolo Abeni <[email protected]>2024-02-27 11:27:20 +0100
commit2322467a0f5d6cf05752092938e6db1250a0b28e (patch)
tree903f4129e1d6c948bb6cb64e91f4f972970b01c9 /scripts/generate_rust_analyzer.py
parent58cc8640b627558ffd1e6c5c415ff034688e3569 (diff)
net: ethernet: adi: adin1110: Reduce the MDIO_TRDONE poll interval
In order to do a clause 22 access to the PHY registers of the ADIN1110, we have to write the MDIO frame to the ADIN1110_MDIOACC register, and then poll the MDIO_TRDONE bit (for a 1) in the same register. The device will set this bit to 1 once the internal MDIO transaction is done. In practice, this bit takes ~50 - 60 us to be set. The first attempt to poll the bit is right after the ADIN1110_MDIOACC register is written, so it will always be read as 0. The next check will only be done after 10 ms, which will result in the MDIO transactions taking a long time to complete. Reduce this polling interval to 100 us. Since this interval is short enough, switch the poll function to readx_poll_timeout_atomic() instead. Reviewed-by: Nuno Sa <[email protected]> Signed-off-by: Ciprian Regus <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
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