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authorDavid Lechner <[email protected]>2023-12-04 11:33:29 -0600
committerMark Brown <[email protected]>2023-12-06 14:19:31 +0000
commit1fc8dc5721bbc7a21cb4cc60c35eb8031942542b (patch)
tree07231018945c2c81cf33b54a54340d1650c99d4c /scripts/generate_rust_analyzer.py
parent9d023ecc31859c7f7c8ca27b5fec52b2dbb8086f (diff)
spi: axi-spi-engine: remove spi_engine_get_clk_div()
Now that host->max_speed_hz and xfer->effective_speed_hz are properly set, we can use them instead of having to do more complex calculations to get the clock divider for each transfer. This removes the spi_engine_get_clk_div() function and replaces it with just dividing the two clock rates. Since the hardware register value is the divider minus one, we need to subtract one. Subtracting one was previously done in the spi_engine_get_clk_div() function. Signed-off-by: David Lechner <[email protected]> Acked-by: Michael Hennerich <[email protected]> Acked-by: Nuno Sa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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