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| author | Inochi Amaoto <[email protected]> | 2024-01-26 17:20:00 +0800 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2024-01-26 13:33:52 +0100 |
| commit | 1f4a994be2c3d13852fd5c1054f292bd303352cc (patch) | |
| tree | 119de831be5569a5c7422c2ac0f98a9b1df57c0c /scripts/generate_rust_analyzer.py | |
| parent | 0d1d824a4ac102db35bc8524a8be97ada8ad37ab (diff) | |
riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format
Change the timer layout in the dtb to fit the format that needed by
the SBI.
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Reviewed-by: Chen Wang <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions