diff options
| author | Chris Morgan <[email protected]> | 2023-10-18 10:33:55 -0500 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2023-11-16 21:26:06 +0100 |
| commit | 1af27671f62ce919f1fb76082ed81f71cb090989 (patch) | |
| tree | d16a0863a47c96aa8672fd497ec753b86e063858 /scripts/generate_rust_analyzer.py | |
| parent | b85ea95d086471afb4ad062012a4d73cd328fa86 (diff) | |
clk: rockchip: rk3568: Add PLL rate for 292.5MHz
Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel
can run at a requested 60hz (59.96, close enough).
I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."
Signed-off-by: Chris Morgan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions